1. Field of the Invention
The present invention relates to a memory device utilizing a memory element, and a manufacturing method thereof.
2. Description of the Related Art
In recent years, with the widespread use of electronic devices such as personal computers and mobile phones, demand for higher performance of electronic devices has been increased. In order to achieve higher performance of such electronic devices, higher integration and larger capacity of memories have been particularly required in addition to higher-speed operation of memories and interfaces, improvement in processing performance of external devices, and the like.
The “memory” used here includes, in its category, not only a main memory for storing data and program but also a register, a cache memory, and the like used in a microprocessor unit (MPU). A register is provided to temporarily hold data for carrying out arithmetic processing, holding a program execution state, or the like. In addition, a cache memory is located between an arithmetic circuit and a main memory in order to reduce low-speed access to the main memory and speed up the arithmetic processing. In a memory device such as a register or a cache memory, writing of data needs to be performed at higher speed than in a main memory. Thus, in general, a flip-flop or the like is used as a register, and a static random access memory (SRAM) or the like is used as a cache memory.
A memory cell (also referred to as memory element) in an SRAM includes a latch circuit which stores one-bit data and two access transistors (nMOSFETs). The latch circuit includes a pair of driver transistors (nMOSFETs) and a pair of load transistors (pMOSFETs). In the SRAM, such memory cells are arranged in a matrix, and the potentials of a word line and a bit line are controlled so that data reading, data writing, and data erasing are performed for a specific memory cell.
The SRAM stores data using the operation state of a latch to which power is continuously supplied (i.e., which of a pair of cross-connected transistors is on/off state). Unlike a DRAM, the SRAM does not need refresh operation; thus, the SRAM consumes only a minimum amount of power supply current necessary for holding the operation state of the latch circuit. However, with miniaturization of SRAMs, a problem of an increase in power consumption due to leakage current arises. For example, it has been reported that the use of a pair of capacitors instead of a pair of load transistors leads to a reduction in power consumption (Patent Document 1). However, along with a further increase in capacity of memories, an increase in power consumption due to leakage current might be caused.
Furthermore, since the SRAM is volatile, data is lost when power supply is stopped; therefore, an additional memory device using a magnetic material or an optical material is needed in order to hold data for a long time. In recent years, attention has been directed to, as one measure to conserve energy, a normally-off computer in which data is not lost even after power supply is stopped and which returns to an operation mode shortly after power is turned on. It is essential to achieve higher performance of a nonvolatile logic and a nonvolatile memory.